Efficient Implementation of Error Detection Functions

As semiconductor technology advances, the size of the transistors is shrinking. This technology has reached a point where the potential of transient errors is becoming significant even for combinational logic. Previous efforts to detect such errors have used a general approach applied to the entire circuit. In this project, the error detection efforts are tailored to the specifics of the targeted circuit. A new measure of error susceptibility is defined which provides for simpler tradeoff analysis. The critical path of the circuit, with low threshold transistors, is analyzed first as the most likely starting point, followed by other parts of the circuit with high error susceptibility. This approach is shown to be efficient for error detection and provides valuable tradeoff input to the designer of error detection circuits. The error handling is detection only, not correction or prevention, placing the responsibility for correction on the system software.